The present invention relates generally to semiconductor memories, and more particularly, to a switchable bit-line pair Via ROM (Via-programmable Read-Only Memory) that has no dummy poly gate and has a high sensing speed.
Conventional Via ROMs require dummy poly gates for diffusion isolation as shown in FIG. 1, which is a circuit diagram illustrating a 4×4 Via ROM of the prior art. Each transistor has a first terminal connected to a reference voltage (e.g. a ground voltage) and a second terminal connected to one of four word-lines. Most importantly, each transistor has a third terminal for storing data according to whether the terminal is connected to one of four bit-lines through a Via contact. Bit-lines 0-3 are represented as “BL0-BL3”, and word-lines 0-3 are represented as “WL0-WL3”. FIG. 2 illustrates a layout of the 4×4 Via ROM shown in FIG. 1. The effective bit-cell size needs to be 1.5 poly-pitch on average as a result of the extra dummy poly gates. In addition, sensing speed and device local variations of the conventional Via ROMs need to be strengthened to comply with the trend of high speed ROMs.